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Merge acccd75e7d into eeb39a0b2b

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Elisha Hollander 2026-02-06 11:23:32 +00:00 committed by GitHub
commit 52f8e4d063
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1 changed files with 1 additions and 31 deletions
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32
src/core/vendor/DisassembleX86-64.mjs vendored
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@ -246,7 +246,7 @@ const Mnemonics = [
["ROL","ROR","RCL","RCR","SHL","SHR","SAL","SAR"],
["ROL","ROR","RCL","RCR","SHL","SHR","SAL","SAR"],
["ROL","ROR","RCL","RCR","SHL","SHR","SAL","SAR"],
"AAMB","AADB","???",
"AAM","AAD","SALC",
"XLAT",
/*------------------------------------------------------------------------------------------------------------------------
X87 FPU.
@ -4751,36 +4751,6 @@ function DecodePrefixAdjustments()
return(null);
}
}
//The L1OM vector prefix settings decoding.
if( Opcode === 0xD6 )
{
//-------------------------------------------------------------------------------------------------------------------------
Opcode = BinCode[CodePos]; //read L1OM byte settings.
NextByte(); //Move to the next byte.
//-------------------------------------------------------------------------------------------------------------------------
Opcode |= ( BinCode[CodePos] << 8 ); //Read next L1OM byte settings.
NextByte(); //Move to the next byte.
//-------------------------------------------------------------------------------------------------------------------------
WidthBit = SIMD & 1;
VectorRegister = ( Opcode & 0xF800 ) >> 11;
RoundMode = VectorRegister >> 3;
MaskRegister = ( Opcode & 0x0700 ) >> 8;
HInt_ZeroMerg = ( Opcode & 0x0080 ) >> 7;
ConversionMode = ( Opcode & 0x0070 ) >> 4;
RegExtend = ( Opcode & 0x000C ) << 1;
BaseExtend = ( Opcode & 0x0003 ) << 3;
IndexExtend = ( Opcode & 0x0002 ) << 2;
//-------------------------------------------------------------------------------------------------------------------------
Opcode = 0x700 | BinCode[CodePos]; //read the 8 bit opcode.
NextByte(); //Move to the next byte.
//-------------------------------------------------------------------------------------------------------------------------
return(null);
}
//Only decode L1OM instead of MVEX/EVEX if L1OM compatibility mode is set.